In fabrication of semiconductor components and devices, as sizes of the components and devices decrease, challenges increase. In particular, pitch size of interconnecting lines and gaps of components and devices are evolving from 18 nanometers (nm) to sub 14 nm half-pitch size, creating smaller or tighter pitch metal trenches used for wire connections. A problem with smaller/tighter pitch sizes is the introduction of capacitive coupling between interconnecting lines. A solution to address capacitive coupling is to remove or relocate an interconnecting line. Another solution is to provide air gaps between interconnecting lines.
Fabrication of semiconductor components and devices includes indirect patterning or lithographic methods; however, it is a challenge to create air gaps using indirect patterning or lithography. It further becomes more of challenge when designs use interlayer dielectric (ILD) structures. In particular, as components and devices become smaller, the challenge increases as to providing such air gaps using indirect patterning or lithographic methods.